Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand‑in‑hand with Front‑End teams, we transform cutting‑edge designs into industry‑leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact Drive Cisco's silicon innovation by performing comprehensive chip‑level EMIR and ESD analysis to ensure the reliability of our next‑generation designs. Investigate complex EMIR and ESD results to propose and implement effective optimizations that maintain design integrity. Collaborate with package teams and block owners to guide design fixes and ensure robust power grid performance. Coordinate with EDA tool vendors and flow teams to enhance the accuracy and scalability of our sign‑off methodologies. Contribute to the end‑to‑end physical implementation process to ensure our silicon solutions meet the highest standards for performance and reliability before tape‑out. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of hands‑on experience in ASIC design and verification. Strong understanding of schematics and layout in FinFET technologies. Experience in deep submicron CMOS technologies. Hands‑on experience in RTL‑to‑GDSII flow, floorplanning, and power planning. Preferred Qualifications Good knowledge of ESD protection concepts and implementation. Familiarity with PnR and verification tools such as Synopsys, Cadence, or Siemens. Strong scripting skills in Python, TCL, or Bash. Ability to collaborate effectively with cross‑functional teams and external vendors. Experience in full‑chip physical design and tape‑out processes. #J-18808-Ljbffr